Display device and method of manufacturing the same

ABSTRACT

A display device includes a display panel. The display panel includes a transistor, an insulating layer disposed on the transistor, a light emitting element electrically connected to the transistor and including a first electrode disposed on the insulating layer, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer, a stopper pattern disposed spaced apart from the first electrode, a pixel definition layer provided on the stopper pattern. A first opening extends through the pixel definition layer to the first electrode, and a second opening extends through the pixel defining layer to the stopper pattern. A thin film encapsulation layer disposed on the pixel definition layer and inside the second opening, covering the light emitting element.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This U.S. Non-Provisional Pat. Application claims priority under 35U.S.C. § 119 of Korean Patent Application No. 10-2021-0176440, filed onDec. 10, 2021, the contents of which are hereby incorporated byreference in its entirety.

BACKGROUND 1. Field of Disclosure

The present disclosure relates to a display device and a method ofmanufacturing the same. More particularly, the present disclosurerelates to a display device including a pixel definition layer and amethod of manufacturing the display device.

2. Description of the Related Art

Display devices, such as smartphones, tablet computers, notebookcomputers, car navigation devices, smart televisions, are beingdeveloped. The display devices include a display device to provideinformation.

In the display device, a reflection phenomenon caused by an externalnatural light occurs. Due to the reflection phenomenon, a visibility ofthe display device is lowered. The display device includes an opticalfilm to prevent the occurrence of the reflection phenomenon.

SUMMARY

The present disclosure provides a display device having improvedstrength against shear stress.

The present disclosure provides a method of manufacturing the displaydevice.

In one aspect, the inventive concept provides a display device includinga display panel. The display panel includes a transistor, an insulatinglayer disposed on the transistor, a light emitting element, a stopperpattern, a pixel definition layer, and a thin film encapsulation layer.The light emitting element is electrically connected to the transistorand includes a first electrode disposed on the insulating layer, a lightemitting layer disposed on the first electrode, and a second electrodedisposed on the light emitting layer. The stopper pattern is disposedspaced apart from the first electrode. The pixel definition layer isprovided on the stopper pattern. The pixel definition layer has a firstopening extends through the pixel definition layer to the firstelectrode and a second opening extends through the pixel defining layerto the stopper pattern. The thin film encapsulation layer is disposed onthe pixel definition layer and inside the second opening, and covers thelight emitting element.

The stopper pattern is disposed on the insulating layer and includes asame material as the first electrode.

The stopper pattern has a same layered structure as the first electrode.

The second electrode is disposed inside the second opening.

The thin film encapsulation layer includes a first inorganic layer, anorganic layer disposed on the first inorganic layer, and a secondinorganic layer disposed on the organic layer.

The stopper pattern is provided in plural, the second opening isprovided in plural, and there is one of the stopper patterns at a baseof the second openings.

The light emitting element includes a plurality of first color lightemitting elements, a plurality of second color light emitting elements,and a plurality of third color light emitting elements. The stopperpattern is disposed in a non-light-emitting area defined between onelight emitting element among the first color light emitting elements,the second light emitting elements adjacent to each other among thesecond color light emitting elements, and one light emitting elementamong the third color light emitting elements.

The stopper pattern is provided in plural, and two or more stopperpatterns are disposed in the non-light-emitting area.

The pixel definition layer includes a first area having a firstthickness and a second area having a second thickness smaller than thefirst thickness.

The second opening is defined in each of the first area and the secondarea.

The second opening defined in the second area further extends throughthe insulating layer.

The second opening has a depth greater than a width.

The display device further includes a connection electrode disposedbetween the transistor and the light emitting element and electricallyconnected to the transistor and the light emitting element. The stopperpattern is disposed under the insulating layer and include the samematerial as the connection electrode.

The transistor includes a semiconductor pattern and a gate, and thestopper pattern is disposed under the insulating layer and includes thesame material as the gate.

The display device further includes an input sensor disposed on thedisplay panel.

The display device further includes an anti-reflective unit disposed onthe input sensor. The anti-reflective unit includes a color filteroverlapping the first opening and a light blocking pattern overlappingthe second opening.

In another aspect, the inventive concept provides a method ofmanufacturing a display device. The method includes forming a stopperpattern, forming a first electrode of a light emitting element spacedapart from the stopper pattern, forming a pixel definition layer on theinsulating layer, the stopper pattern, and the first electrode; forminga first opening through the pixel definition layer to expose the firstelectrode of the light emitting element and remove some of the pixeldefinition layer covering the stopper pattern, providing a mask patternon the pixel definition layer, wherein the mask pattern has an etchingopening that corresponds to the stopper pattern, forming a secondopening through the pixel definition layer to expose the stopperpattern, removing the mask pattern, forming a light emitting layer and asecond electrode on the first electrode of the light emitting element,and forming a thin film encapsulation layer on the second electrode. Thestopper pattern is formed prior to the first electrode of the lightemitting element or is formed through the same process as the firstelectrode of the light emitting element. The mask pattern includes atransparent conductive oxide.

The second electrode is disposed inside the second opening.

The method further includes forming an inorganic layer on the secondelectrode and inside the second opening.

The method further includes forming a transistor and forming aconnection electrode electrically connected to the transistor and thefirst electrode of the light emitting element. The stopper pattern isformed through a same process as a gate of the transistor or theconnection electrode.

According to the above, as the thin film encapsulation layer is disposedin the second opening of the pixel definition layer, an adhesion of thethin film encapsulation layer with respect to a structure disposedthereunder is improved. Thus, a durability against a shear stress isimproved.

The stopper pattern is disposed to overlap the second opening, and thus,a depth of the second opening is controlled. As the stopper pattern isformed through the same process as a conductive pattern of the displaypanel, an additional process is not required to process the stopperpattern.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the present disclosure will becomereadily apparent by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings wherein:

FIGS. 1A to 1C are perspective views of a display device according to anembodiment of the present disclosure;

FIG. 2 is a cross-sectional view of a display device according to anembodiment of the present disclosure;

FIG. 3 is a plan view of a display area of a display device according toan embodiment of the present disclosure;

FIG. 4 is a cross-sectional view of a display device taken along a lineI-I′ of FIG. 3 ;

FIGS. 5A and 5B are plan views of a display area of a display panelaccording to embodiments of the present disclosure;

FIG. 6 is a cross-sectional view taken along a line II-II′ of FIG. 5A;

FIGS. 7A to 7F are cross-sectional views of a method of manufacturing adisplay device according to an embodiment of the present disclosure; and

FIGS. 8 and 9 are cross-sectional views of a display panel according toembodiments of the present disclosure.

DETAILED DESCRIPTION

In the present disclosure, it will be understood that when an element(or area, layer, or portion) is referred to as being “on”, “connectedto” or “coupled to” another element or layer, it can be directly on,connected or coupled to the other element or layer or interveningelements or layers may be present.

Like numerals refer to like elements throughout. In the drawings, thethickness, ratio, and dimension of components are exaggerated foreffective description of the technical content. As used herein, the term“and/or” may include any and all combinations of one or more of theassociated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another element. Thus, a first element discussed belowcould be termed a second element without departing from the teachings ofthe present disclosure. As used herein, the singular forms, “a”, “an”and “the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper” and the like, may be used herein for ease of description todescribe one element or feature’s relationship to another elements orfeatures as shown in the figures.

It will be further understood that the terms “includes” and/or“including”, when used in this specification, specify the presence ofstated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

Unless otherwise defined, all terms including technical and scientificterms used herein have the same meaning as commonly understood by one ofordinary skill in the art to which this disclosure belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Hereinafter, embodiments of the present disclosure will be describedwith reference to accompanying drawings.

FIGS. 1A to 1C are perspective views of a display device DD according toan embodiment of the present disclosure.

Referring to FIGS. 1A to 1C, a display surface DD-IS may besubstantially parallel to a plane defined by a first directional axisDR1 and a second directional axis DR2. A third directional axis DR3 mayindicate a normal line direction that is orthogonal to the displaysurface DD-IS, and may also be referred to as a “thickness direction” ofthe display device DD. Front (or upper) and rear (or lower) surfaces ofeach member may be distinguished from each other with respect to thethird directional axis DR3. Hereinafter, first, second, and thirddirections may correspond to directions respectively indicated by thefirst, second, and third directional axes DR1, DR2, and DR3 and may beassigned with the same reference numerals as the first, second, andthird directional axes DR1, DR2, and DR3 .

As shown in FIGS. 1A to 1C, the display surface DD-IS may include adisplay area DD-DA that displays an image IM and a non-display areaDD-NDA adjacent to the display area DD-DA. The image IM may not bedisplayed through the non-display area DD-NDA. FIGS. 1A to 1C show iconimages as a representative example of the image IM. As an example, thedisplay area DD-DA may have a quadrangular shape. The non-display areaDD-NDA may surround the display area DD-DA; however, this is not alimitation o the disclosure. The shape of the display area DD-DA and theshape of the non-display area DD-NDA may be designed in other ways inrelation to each other.

As shown in FIGS. 1A to 1C, the display device DD may include aplurality of areas defined according to its operation state. The displaydevice DD may include a folding area that includes a folding axis FX, afirst flat area NFA1, and a second flat area NFA2. The folding area maybe an area that substantially forms a curvature upon folding, asillustrated in FIG. 1B and FIG. 1C. The first flat area NFA1 and thesecond flat area NFA2 remain planar upon folding.

In the present embodiment, the display device DD provided with thefolding axis FX substantially parallel to a major axis thereof is shownas a representative example. However, the present disclosure should notbe limited thereto or thereby, and the folding axis FX may besubstantially parallel to a minor axis of the display device DD.According to an embodiment, the display device DD may have a bar shapethat is not folded.

Referring to FIG. 1B, the display device DD may be folded inwardly(inner-folding or inner-bending) such that the display surface DD-IS ofthe first flat area NFA1 may face the display surface DD-IS of thesecond flat area NFA2. Referring to FIG. 1C, the display device DD maybe folded outwardly (outer-folding or outer-bending) such that thedisplay surface DD-IS (both the first flat area NFA1 and the second flatarea NFA2) may be exposed to the outside.

According to an embodiment, the display device DD may include aplurality of folding areas FA. In addition, the folding areas FA may bedefined corresponding to a manner in which a user operates the displaydevice DD. For instance, the folding area FA may be defined in adiagonal direction crossing the first directional axis DR1 and thesecond directional axis DR2 when viewed in a plane. The folding area FAmay have a size determined depending on a radius of curvature withoutbeing fixed. According to an embodiment of the present disclosure, thedisplay device DD may repeat only the operation mode illustrated inFIGS. 1A and 1B or may repeat only the operation mode illustrated inFIGS. 1A and 1C.

In the present embodiment, a foldable display device DD is shown as arepresentative example and should not be a limitation. The displaydevice DD may be a flat display device or a rollable display device. Inthe present embodiment, the display device DD applied to a mobile phoneis illustrated as a representative example. However, it should not beparticularly limited. According to an embodiment, the display device DDmay be incorporated into a large-sized electronic item, such as atelevision set and a monitor, and a small- and medium-sized electronicitem, such as a tablet computer, a car navigation unit, a game unit, anda smart watch.

FIG. 2 is a cross-sectional view of the display device DD according toan embodiment of the present disclosure. FIG. 2 shows a cross-sectiondefined by the second directional axis DR2 and the third directionalaxis DR3.

According to an embodiment, the display device DD may include a displaypanel DP, an input sensor ISL, an anti-reflective unit RPL, and a windowWP. At least some components of the display panel DP, the input sensorISL, the anti-reflective unit RPL, and the window WP may be formedthrough successive processes or may be attached to each other by anadhesive member.

Among the input sensor ISL, the anti-reflective unit RPL, and the windowWP, a component that is formed through successive processes with anothercomponent is referred to as a “layer”. Among the input sensor ISL, theanti-reflective unit RPL, and the window WP, a component that is coupledto another component by the adhesive member is referred to as a “panel”.The panel includes a base layer providing a base surface, e.g., asynthetic resin film, a composite material film, or a glass substrate,however, the base layer may be omitted from the component that isreferred to as the “layer”. In other words, the component that isreferred to as the “layer” is disposed on the base surface provided byanother component. The input sensor, the anti-reflective unit, and thewindow may be respectively referred to as an input sensing panel, ananti-reflective panel, and a window panel, or an input sensing layer, ananti-reflective layer, and a window layer depending on the presence orabsence of the base layer.

As shown in FIG. 2 , the display device DD may include a display panelDP, an input sensing layer ISL, an anti-reflective layer RPL, and awindow panel WP. The input sensing layer ISL may be disposed directly onthe display panel DP. In the present disclosure, the expression “acomponent B1 is disposed directly on a component A1” means that noadhesive members are present between the component B1 and the componentA1. The component B1 may be formed on a base surface provided by thecomponent A1 through successive processes after the component A1 isformed.

The display panel DP may generate the image, and the input sensing layerISL may obtain coordinate information of the external input (e.g., atouch event). Although not shown in figures, a protective member may befurther disposed under the display panel DP. The protective member maysupport the display panel DP and may protect the display panel DP fromexternal impacts.

The display panel DP may be a light emitting type display panel.However, this is not a limitation of the disclosure. For instance, thedisplay panel DP may be an organic light emitting display panel or aquantum dot light emitting display panel. A light emitting layer of theorganic light emitting display panel may include an organic lightemitting material. A light emitting layer of the quantum dot lightemitting display panel may include a quantum dot and/or a quantum rod.Hereinafter, the organic light emitting display panel will be describedas a representative example of the display panel DP.

The anti-reflective layer RPL may reduce a reflectance with respect to anatural light (or a sunlight) incident thereto from above the windowpanel WP. According to an embodiment, the anti-reflective layer RPL mayinclude a base layer and color filters. The color filters may have apredetermined arrangement. The arrangement of the color filters may bedetermined by taking into account emission colors of pixels included inthe display panel DP. The anti-reflective layer RPL may further includea light blocking pattern disposed adjacent to the color filters.

Although shown schematically in figures, the window panel WP may includea base layer and a bezel pattern. The bezel pattern may define a bezelarea of the display device DD, i.e., the non-display area DD-NDA (referto FIG. 1A).

According to an embodiment, an adhesive layer may be disposed betweenthe input sensing layer ISL and the anti-reflective layer RPL. Accordingto an embodiment, the window panel WP may be disposed directly on theanti-reflective layer RPL.

FIG. 3 is a plan view of the display area DD-DA of the display deviceaccording to an embodiment of the present disclosure.

Referring to FIG. 3 , a plurality of pixel areas PXA-R, PXA-G1, PXA-G2,and PXA-B may be arranged in the display area DD-DA. A peripheral areaNPXA may be defined adjacent to the pixel areas PXA-R, PXA-G1, PXA-G2,and PXA-B. The peripheral area NPXA may define a boundary of the pixelareas PXA-R, PXA-G1, PXA-G2, and PXA-B and may prevent a color mixturebetween the pixel areas PXA-R, PXA-G1, PXA-G2, and PXA-B. The pixelareas PXA-R, PXA-G1, PXA-G2, and PXA-B may define a plurality of pixelrows PXL-1 and PXL-2 extending in the second direction DR2. In FIG. 3 ,the second direction DR2 may be defined as an extension direction of thepixel rows PXL-1 and PXL-2 or a row direction, and the first directionDR1 may be defined as a column direction.

In the present embodiment, the pixel rows PXL-1 and PXL-2 may beclassified into two groups. A first group of pixel rows PXL-1 mayinclude a first color pixel area PXA-R generating a first color lightand a second color pixel area PXA-B generating a second color light. Thefirst color pixel areas PXA-R may be alternately arranged with thesecond color pixel areas PXA-B in the row direction DR2. The first groupof pixel rows PXL-1 may include a first pixel row PXL-11 and a secondpixel row PXL-12. The first pixel rows PXL-11 may be alternatelyarranged with the second pixel rows PXL-12 in the column direction DR1.

The first color pixel areas PXA-R and the second color pixel areas PXA-Bof the first pixel row PXL-11 may be arranged differently from the firstcolor pixel areas PXA-R and the second color pixel areas PXA-B of thesecond pixel row PXL-12. In the column direction DR1, the first colorpixel area PXA-R of the first pixel row PXL-11 may be aligned with thesecond color pixel area PXA-B of the second pixel row PXL-12, and thesecond color pixel area PXA-B of the first pixel row PXL-11 may bealigned with the first color pixel area PXA-R of the second pixel rowPXL-12.

A second group of pixel rows PXL-2 may include third color pixel areasPXA-G1 and PXA-G2 generating a third color light. The third color pixelareas PXA-G1 and PXA-G2 may be classified into two types of pixel areas,which include the light emitting areas with different shapes when viewedin a plane. When a first type area PXA-G1 is rotated at about 90 degreesin the plane, the first type area PXA-G1 may have substantially the sameshape as that of a second type area PXA-G2. The first type area PXA-G1may have a shape extending in a first cross direction DDR1, and thesecond type area PXA-G2 may have a shape extending in a second crossdirection DDR2 crossing the first cross direction DDR1.

The first type areas PXA-G1 may be alternately arranged with the secondtype areas PXA-G2 in the row direction DR2. The second group of pixelrows PXL-2 may include a third pixel row PXL-21 and a fourth pixel rowPXL-22. The third pixel rows PXL-21 may be alternately arranged with thefourth pixel rows PXL-22 in the column direction DR1.

The first type areas PXA-G1 and the second type areas PXA-G2 of thethird pixel row PXL-21 may be arranged differently from the first typeareas PXA-G1 and the second type areas PXA-G2 of the fourth pixel rowPXL-22. In the column direction DR1, the first type areas PXA-G1 of thethird pixel row PXL-21 may be aligned with the second type areas PXA-G2of the fourth pixel row PXL-22, and the second type areas PXA-G2 of thethird pixel row PXL-21 may be aligned with the first type areas PXA-G1of the fourth pixel row PXL-22. However, they should not be limitedthereto or thereby, and the second group of pixel rows PXL-2 may includepixel areas of one type having the light emitting area of the same shapewhen viewed in the plane.

The first group of pixel rows PXL-1 may be alternately arranged with thesecond group of pixel rows PXL-2 in the column direction DR1. One of thethird pixel row PXL-21 and the fourth pixel row PXL-22 may be disposedbetween the first pixel row PXL-11 and the second pixel row PXL-12,which are consecutive to each other, and the other of the third pixelrow PXL-21 and the fourth pixel row PXL-22 may be disposed between thesecond pixel row PXL-12 and another first pixel row PXL-11 that isconsecutive to the second pixel row PXL-12.

In the present embodiment, the first color pixel area PXA-R, the secondcolor pixel area PXA-B, and the third color pixel areas PXA-G1 andPXA-G2, which have different sizes in the planes, are shown as arepresentative example. The disclosure is not limited to the exampleprovided. Among the light emitting areas, the size of the second colorpixel area PXA-B has the greatest size, and the size of the third colorpixel areas PXA-G1 and PXA-G2 has the smallest size, however, theyshould not be limited thereto or thereby.

In the present embodiment, the first color pixel area PXA-R may generatea red light, the second color pixel area PXA-B may generate a bluelight, and the third color pixel areas PXA-G1 and PXA-G2 may generate agreen light. The disclosure is not be limited to the embodiment that isprovided. According to an embodiment, the color lights emitted from thefirst color pixel area PXA-R, the second color pixel area PXA-B, and thethird color pixel areas PXA-G1 and PXA-G2 may be selected as acombination of three color lights that may generate a white light whenbeing mixed.

FIG. 4 is a cross-sectional view of the display device DD taken along aline I-I′ of FIG. 3 .

Hereinafter, a stack structure of the display device DD will bedescribed based on a cross-section corresponding to the first colorpixel area PXA-R. As shown in FIG. 4 , the display device DD may includethe display panel DP, the input sensing layer ISL, and theanti-reflective layer RPL, which are formed through sequentialprocesses.

The display panel DP is illustrated focusing on a light emitting elementLD and a transistor TFT electrically connected to the light emittingelement LD. The transistor TFT may be one of a plurality of transistorsincluded in a driving circuit of the pixel. In the present embodiment,the transistor TFT will be described as a silicon transistor, however,according to an embodiment, the transistor TFT may be a metal oxidetransistor. According to an embodiment, the driving circuit of the pixelmay include both the silicon transistor and the metal oxide transistor.

A barrier layer 10 br may be disposed on a base layer 110. The barrierlayer 10 br may prevent a foreign substance from entering the displaydevice DD from the outside. The barrier layer 10 br may include at leastone inorganic layer. The barrier layer 10 br may include a silicon oxidelayer and a silicon nitride layer. Each of the silicon oxide layer andthe silicon nitride layer may be provided in plural, and the siliconoxide layers and the silicon nitride layers may be alternately stackedwith each other.

A shielding electrode BMLa may be disposed on the barrier layer 10 br.The shielding electrode BMLa may include a metal material. The shieldingelectrode BMLa may include molybdenum (Mo), an alloy includingmolybdenum (Mo), titanium (Ti), or an alloy including titanium (Ti),which has a good heat resistance. The shielding electrode BMLa mayreceive a bias voltage. The shielding electrode BMLa may receive a firstpower source voltage ELVDD. The shielding electrode BMLa may prevent anelectric potential caused by a polarization phenomenon from exertinginfluence on the silicon transistor TFT. The shielding electrode BMLamay prevent an external light from reaching the transistor TFT.According to an embodiment, the shielding electrode BMLa may be afloating electrode isolated from other electrodes or lines.

A buffer layer 10 bf may be disposed on the barrier layer 10 br. Thebuffer layer 10 bf may prevent metal atoms or impurities from beingdiffused to a semiconductor pattern SP disposed thereon from the baselayer 110. The buffer layer 10 bf may include at least one inorganiclayer. The buffer layer 10 bf may include a silicon oxide layer and asilicon nitride layer.

The semiconductor pattern SP may be disposed on the buffer layer 10 bf.The semiconductor pattern SP may include a silicon semiconductor. As anexample, the silicon semiconductor may include amorphous silicon orpolycrystalline silicon. For example, the semiconductor pattern SP mayinclude low temperature polycrystalline silicon.

The semiconductor pattern SP may have different electrical propertiesdepending on whether it is doped or not or doped with an N-type dopantor a P-type dopant. The semiconductor pattern SP may include ahigh-doped region having a relatively high conductivity and a low-dopedregion having a relatively low conductivity. The high-doped region maybe doped with an N-type dopant or a P-type dopant. A P-type transistormay include a doped region doped with the P-type dopant, and an N-typetransistor may include a doped region doped with the N-type dopant. Thelow-doped region may be a non-doped region or a region doped at aconcentration lower than that of the high-doped region.

The high-doped region may substantially serve as an electrode or asignal line. The low-doped region may substantially correspond to achannel area (or an active area) of the transistor. In other words, aportion of the semiconductor pattern SP may be a channel of thetransistor, another portion of the semiconductor pattern may be a sourceor a drain of the transistor, and the other portion of the semiconductorpattern may be a connection electrode or a connection signal line.

A source area SE1, a channel area AC1 (or an active area), and a drainarea DE1 of the transistor TFT may be formed from the semiconductorpattern SP. The source area SE1 and the drain area DE1 may extend inopposite directions to each other from the active area AC1 in across-section.

A first insulating layer 10 may be disposed on the buffer layer 10 bf.The first insulating layer 10 may cover the semiconductor pattern SP.The first insulating layer 10 may include an inorganic layer. The firstinsulating layer 10 may include at least one of aluminum oxide, titaniumoxide, silicon oxide, silicon nitride, silicon oxynitride, zirconiumoxide, and hafnium oxide.

The first insulating layer 10 may have a single-layer structure of asilicon oxide layer, but this is not a limitation of the disclosure. Notonly the first insulating layer 10, but also an inorganic layer of acircuit layer 120 described later may have a single-layer or multi-layerstructure. The inorganic layer may include at least one of theabove-mentioned materials. The structure or the materials describedabove are examples and not limitations of the disclosure.

A gate GT1 of the transistor TFT may be disposed on the first insulatinglayer 10. The gate GT1 may be a portion of a metal pattern. The gate GT1may overlap the channel area AC1. The gate GT1 may be used as a mask ina process of doping the semiconductor pattern SP. The gate GT1 mayinclude molybdenum (Mo), an alloy including molybdenum (Mo), titanium(Ti), an alloy including titanium (Ti), or the like, which has a goodheat resistance. These materials are examples, not limitations of thedisclosure.

A first electrode CE10 of a storage capacitor Cst may be disposed on thefirst insulating layer 10. In FIG. 4 , the gate GT1 and the firstelectrode CE10 are spaced apart from each other. In other embodiments,the first electrode CE10 may extend from the gate GT1 when viewed in aplane and may be provided integrally with the gate GT1.

In the present embodiment, the gate GT1 and the first electrode CE10 maybe formed through the same process. Accordingly, the gate GT1 and thefirst electrode CE10 may include the same material and may have the samestructure.

A second insulating layer 20 may be disposed on the first insulatinglayer 10 and may cover the gate GT1 and the first electrode CE10. Thesecond insulating layer 20 may include at least one of aluminum oxide,titanium oxide, silicon oxide, silicon nitride, silicon oxynitride,zirconium oxide, and hafnium oxide. The second insulating layer 20 mayhave a multi-layer structure of inorganic layers.

A second electrode CE20 of the storage capacitor Cst may be disposed onthe second insulating layer 20. The third insulating layer 30 may bedisposed on the second insulating layer 20. A third insulating layer 30may cover the second electrode CE20 of the storage capacitor Cst.

A first connection electrode CNE1 may be disposed on the thirdinsulating layer 30. The first connection electrode CNE1 may beconnected to the drain area DE1 of the transistor TFT via a contact holedefined through the first, second, and third insulating layers 10, 20,and 30.

A fourth insulating layer 40 may be disposed on the third insulatinglayer 30. A second connection electrode CNE2 may be disposed on thefourth insulating layer 40. The second connection electrode CNE2 may beconnected to the first connection electrode CNE1 via a contact holedefined through the fourth insulating layer 40. A fifth insulating layer50 may be disposed on the fourth insulating layer 40 and may cover thesecond connection electrode CNE2. Although not shown separately, a dataline may be disposed on the same layer as a layer on which one of thefirst connection electrode CNE1 and the second connection electrode CNE2is disposed.

The layered structure of the first insulating layer 10, the secondinsulating layer 20, the third insulating layer 30, the fourthinsulating layer 40, and the fifth insulating layer 50 is merely anexample, and a conductive layer and an insulating layer may be furtherdisposed in addition to the first insulating layer 10 to the fifthinsulating layer 50.

Each of the fourth insulating layer 40 and the fifth insulating layer 50may include an organic layer. As an example, the organic layer mayinclude a general-purpose polymer such as benzocyclobutene (BCB),polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA),or polystyrene (PS), a polymer derivative having a phenolic group, anacrylic-based polymer, an imide-based polymer, an aryl ether-basedpolymer, an amide-based polymer, a fluorine-based polymer, ap-xylene-based polymer, a vinyl alcohol-based polymer, or blendsthereof.

The light emitting element LD may include a first electrode AE, a lightemitting layer EL, and a second electrode CE. The first electrode AE maybe disposed on the fifth insulating layer 50. The first electrode AE mayinclude a reflective electrode formed. According to an embodiment, thefirst electrode AE may include a reflective layer formed of silver (Ag),magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au),nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compoundsthereof and a transparent or semi-transparent electrode layer formed onthe reflective layer. The transparent or semi-transparent electrodelayer may include at least one selected from the group consisting ofindium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zincoxide (IGZO), zinc oxide (ZnOx), indium oxide (In2O3), andaluminum-doped zinc oxide (AZO). For instance, the first electrode AEmay have a stack structure of ITO/Ag/ITO.

A pixel definition layer PDL may be disposed on the fifth insulatinglayer 50. According to an embodiment, the pixel definition layer PDL mayhave a light absorbing property. For example, the pixel definition layerPDL may have a black color. The pixel definition layer PDL may include abase resin and a black coloring agent mixed with the base resin. Thepixel definition layer PDL may include an acrylic-based resin as thebase resin. The black coloring agent may include a black dye or a blackpigment. The black coloring agent may include a metal material, such ascarbon black, chromium, or an oxide thereof. The pixel definition layerPDL may correspond to a light blocking pattern having a light blockingproperty.

The pixel definition layer PDL may cover a portion of the firstelectrode AE. As an example, a first opening P-OP1 may be definedthrough the pixel definition layer PDL to expose a portion of the firstelectrode AE. The first opening P-OP1 of the pixel definition layer PDLmay define a light emitting area LA-R. An “opening,” as used herein, isintended to mean a discontinuous portion of a layer, such as the pixeldefinition layer PDL, characterized by a regional absence of the layermaterial.

The pixel definition layer PDL may increase a distance between an edgeof the first electrode AE and the second electrode CE. Accordingly, thepixel definition layer PDL may prevent an occurrence of an arc in theedge of the first electrode AE.

Although not shown in figures, a hole control layer may be disposedbetween the first electrode AE and the light emitting layer EL. The holecontrol layer may include a hole transport layer and may further includea hole injection layer. An electron control layer may be disposedbetween the light emitting layer EL and the second electrode CE. Theelectron control layer may include an electron transport layer and mayfurther include an electron injection layer.

A thin film encapsulation layer 140 may be disposed on a light emittingelement layer 130. The thin film encapsulation layer 140 may include aninorganic layer 141, an organic layer 142, and an inorganic layer 143,which are sequentially stacked. However, layers forming the thin filmencapsulation layer 140 should not be limited by these examples.

The inorganic layers 141 and 143 may protect the light emitting elementlayer 130 from moisture and oxygen, and the organic layer 142 mayprotect the light emitting element layer 130 from a foreign substancesuch as dust particles. The inorganic layers 141 and 143 may include asilicon nitride layer, a silicon oxynitride layer, a silicon oxidelayer, a titanium oxide layer, or an aluminum oxide layer. The organiclayer 142 may include an acrylic-based organic layer, however, this isnot a limitation of the disclosure.

Referring to FIG. 4 , the input sensing layer ISL may be disposeddirectly on the thin film encapsulation layer 140. The input sensinglayer ISL may include a first insulating layer 200-IL1, a firstconductive layer 200-CL1, a second insulating layer 200-IL2, a secondconductive layer 200-CL2, and a third insulating layer 200-IL3.According to an embodiment, the first insulating layer 200-IL1 or thethird insulating layer 200-IL3 may be omitted.

Each of the first conductive layer 200-CL1 and the second conductivelayer 200-CL2 may have a single-layer structure or may have amulti-layer structure of layers stacked along the third directional axisDR3. The multi-layered conductive pattern may include at least twolayers among transparent conductive layers and metal layers. Themulti-layered conductive pattern may include the metal layers containingdifferent metal materials from each other. The transparent conductivelayer may include indium tin oxide (ITO), indium zinc oxide (IZO), zincoxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, a metal nanowire, orgraphene. The metal layer may include molybdenum, silver, titanium,copper, aluminum, and alloys thereof. For instance, each of the firstconductive layer 200-CL1 and the second conductive layer 200-CL2 mayhave a three-layer structure of metal layers, e.g., a three-layerstructure of titanium/aluminum/titanium. The metal layers with arelatively high durability and a low reflectance may be provided asupper and lower layers, and the metal layer with a relatively highelectrical conductivity may be provided as an inner layer.

Each of the first conductive layer 200-CL1 and the second conductivelayer 200-CL2 may include a plurality of conductive patterns. The firstconductive layer 200-CL1 may include first conductive patterns, and thesecond conductive layer 200-CL2 may include second conductive patterns.Each of the first conductive patterns and the second conductive patternsmay include sensing electrodes and signal lines connected to the sensingelectrodes. One of the first conductive patterns may be connected to acorresponding second conductive pattern among the second conductivepatterns via a contact hole CH-I defined through the second insulatinglayer 200-IL2. The first conductive patterns and the second conductivepatterns may be disposed to overlap a light blocking pattern 310. Thelight blocking pattern 310 may prevent the external light from beingreflected by the first conductive patterns and the second conductivepatterns.

Each of the first insulating layer 200-IL1, the second insulating layer200-IL2, and the third insulating layer 200-IL3 may include an inorganiclayer or an organic layer. According to an embodiment, the firstinsulating layer 200-IL1 and the second insulating layer 200-IL2 mayinclude the inorganic layer. The third insulating layer 200-IL3 mayinclude the organic layer.

The anti-reflective layer RPL may be disposed directly on the inputsensor layer ISL. The anti-reflective layer RPL may include the lightblocking pattern 310, the color filter 320, and a planarization layer330.

A material for the light blocking pattern 310 should not be limited asalong as the material absorbs light. The light blocking pattern 310 mayhave a black color. The light blocking pattern 310 may include a blackcoloring agent. The black coloring agent may include a black dye or ablack pigment. The black coloring agent may include a metal material,such as carbon black, chromium, or an oxide thereof.

The light blocking pattern 310 may overlap the first conductive patternsand the second conductive patterns. An opening 310-OP may be definedthrough the light blocking pattern 310. The opening 310-OP of the lightblocking pattern 310 may be aligned with the first electrode AE and mayhave a size greater than that of the first opening P-OP1 of the pixeldefinition layer PDL. The opening 310-OP of the light blocking pattern310 may define the pixel area PXA-R. The pixel area PXA-R may correspondto an area from which the light generated by the light emitting elementLD exits to the outside. As the size of the pixel area PXA-R increases,a luminance of the image may increase.

The color filter 320 may overlap at least the pixel area PXA-R. Thecolor filter 320 may further overlap the peripheral area NPXA. A portionof the color filter 320 may be disposed on the light blocking pattern310. The color filter 320 may transmit the light generated by the lightemitting element LD and may block a portion of the external light insome wavelength bands. Accordingly, the color filter 320 may reduce thereflection of the external light, which is caused by the first electrodeAE or the second electrode CE.

The planarization layer 330 may cover the light blocking pattern 310 andthe color filter 320. The planarization layer 330 may include an organicmaterial and may provide a flat upper surface thereon.

FIGS. 5A and 5B are plan views of a display area DP-DA of a displaypanel according to embodiments of the present disclosure. FIG. 6 is across-sectional view taken along a line II-II′ of FIG. 5A.

Referring to FIG. 5A, the first openings P-OP1 of the pixel definitionlayer PDL may define first color light emitting areas LA-R, second colorlight emitting areas LAB, and third color light emitting areas LA-G1 andLA-G2. A first color light emitting element may be disposed in each ofthe first color light emitting areas LA-R, a second color light emittingelement may be disposed in each of the second color light emitting areasLAB, and a third color light emitting element may be disposed in each ofthe third color light emitting areas LA-G1 and LA-G2. An area in whichthe pixel definition layer PDL is disposed may correspond to anon-light-emitting area NLA.

The first color light emitting areas LA-R, the second color lightemitting areas LA-B, and the third color light emitting areas LA-G1 andLA-G2 may correspond to the first color pixel areas PXA-R, the secondcolor pixel areas PXA-B, and the third color pixel areas PXA-G1 andPXA-G2, respectively, shown in FIG. 3 . A relation between the lightemitting area and the pixel area, which correspond to each other, refersto a relation between the first color light emitting area LA-R and thefirst color pixel area PXA-R shown in FIG. 4 .

Second openings P-OP2 may be further defined through the pixeldefinition layer PDL. FIG. 5A shows four second openings P-OP2 arrangedto form one group as a representative example.

One group of the second openings P-OP2 may be disposed in thenon-light-emitting area NLA defined between one first color lightemitting area LA-R, one second color light emitting area LA-B, and twothird color light emitting areas LA-G1 and LA-G2. Groups of the secondopenings P-OP2 may be regularly arranged in rows and columns. The numberof the second openings P-OP2 forming the one group should not beparticularly limited.

FIG. 5B shows second openings P-OP2 having different shape andarrangement from those of the second openings P-OP2 of FIG. 5A as arepresentative example. The second openings P-OP2 may include openingsP-OP21 extending in the first direction DR1 and openings P-OP22extending in the second direction DR2.

The opening P-OP21 extending in the first direction DR1 or the openingPOP22 extending in the second direction DR2 may be disposed in anon-light-emitting area NLA defined between one first color lightemitting area LA-R, one second color light emitting area LA-B, and twothird color light emitting areas LA-G1 and LA-G2. Each of the firstcolor light emitting area LA-R, the second color light emitting areaLA-B, and the third color light emitting areas LA-G1 and LA-G2 may besurrounded by two openings P-OP21 extending in the first direction DR1and two openings P-OP22 extending in the second direction DR2.

Referring to FIG. 6 , the pixel definition layer PDL may have a firstthickness in a first area P-A1 and a second thickness smaller than thefirst thickness in a second area P-A2. The first area P-A1 maycorrespond to a spacer that supports a deposition mask used to form thelight emitting layer EL. The second openings P-OP2 may be defined ineach of the first area P-A1 and the second area P-A2.

Referring to FIG. 6 , the second openings P-OP2 may extend through atleast the pixel definition layer PDL. Each of the second openings P-OP2may expose a stopper pattern STP. In the present embodiment, pluralstopper patterns STP respectively corresponding to the second openingsP-OP2 are shown as a representative example. However, it should not beparticularly limited. The stopper pattern STP may be disposed in eachgroup of the second openings P-OP2 shown in FIG. 5A. For instance, onestopper pattern STP may be disposed to correspond to two second openingsP-OP2 defined in the first area P-A1 of FIG. 6 .

The stopper pattern STP stops the etching of the pixel definition layerPDL in a process of forming the second opening P-OP2, and thus controlsa depth of the second opening P-OP2. In the present embodiment, thestopper pattern STP may be disposed on the fifth insulating layer 50.

In the present embodiment, the stopper pattern STP may be formed throughthe same process as the first electrode AE. The stopper pattern STP mayinclude the same material as that of the first electrode AE. The stopperpattern STP may have the same stack structure as that of the firstelectrode AE. When the first electrode AE has a multi-layer structure ofITO/Ag/ITO, the stopper pattern STP may have the multi-layer structureof ITO/Ag/ITO or a multi-layer structure of ITO/Ag. The reason why thestopper pattern STP has the multi-layer structure of ITO/Ag is becauseITO disposed at an upper portion may be removed in the process offorming the second opening P-OP2 or a subsequent process.

The stopper pattern STP may be disposed spaced apart from the firstelectrode AE when viewed in a plane. Accordingly, a short circuitbetween the first electrodes AE adjacent to each other may be prevented.

At least a portion of the thin film encapsulation layer 140 may bedisposed inside the second opening P-OP2. As show in FIG. 6 , a portionof the inorganic layer 141 may be disposed in the second opening P-OP2.A portion of the organic layer 142 may also be disposed in the secondopening P-OP2. However, this is not a limitation or a requirement of thedisclosure.

A portion of the second electrode CE may also be disposed inside thesecond opening P-OP2. In the second opening P-OP2, the second electrodeCE may be disposed under the inorganic layer 141. Although not shown infigures, in the second opening P-OP2, the electron transport layer andthe hole transport layer disposed under the electron transport layer maybe disposed under the second electrode CE.

As the portion of the second electrode CE is disposed inside the secondopening P-OP2, a coupling force of the second electrode CE with respectto the light emitting element layer 130 may increase. In addition, asthe portion of the inorganic layer 141 is disposed inside the secondopening P-OP2, a coupling force of the inorganic layer 141 with respectto the light emitting element layer 130 may increase. This is because acoupling area between the inorganic layer 141 and the second openingP-OP2 increases.

Due to a tension generated in the inorganic layer 141, a compressiveforce may be applied to an inner surface of the opening P-OP2 by theportion of the inorganic layer 141 disposed inside the opening P-OP2.Accordingly, a coupling force of the inorganic layer 141 with respect tothe inner surface of the opening P-OP2 may increase.

For the above reasons, the second electrode CE and the inorganic layer141 may not be separated from the structure disposed thereunder eventhough the shear stress is applied. Consequently, a durability of thedisplay panel DP against the shear stress may be improved.

The second opening P-OP2 may have a depth greater than its width. Wherethe second opening P-OP2 has a circular shape in plan view as shown inFIG. 5A, the “width” is the diameter, or the maximum distance across thecircle. Where the second opening P-OP2 has a rectangular shape in planview as shown in FIG. 5B, the width is the distance of the shorter side.As the ratio of depth to width increases, the coupling force of thesecond electrode CE and inorganic layer 141 with respect to the secondopening P-OP2 may increase.

A ratio of the width to depth may be 1:1 to 1:3. For instance, a ratioof the width to the depth of the second opening P-OP2 defined in thefirst area P-A1 may be 1:3. A ratio of the diameter to the depth of thesecond opening P-OP2 defined in the second area PA2 may be 1:1.5.However, cases where the width is larger than the depth are not excludedfrom the scope of the present disclosure.

FIGS. 7A to 7F are cross-sectional views of a method of manufacturingthe display device DD according to an embodiment of the presentdisclosure. Hereinafter, the cross-sectional views of FIGS. 7A to 7F areshown with respect to the cross-section of FIG. 6 , and in FIGS. 7A to7F, detailed descriptions of the components described with reference toFIG. 6 will be omitted.

Referring to FIG. 7A, a pixel circuit and the insulating layers 10 br,10 bf, and 10 to 50 may be disposed on the base layer 110. Thetransistor TFT and the capacitor Cst are shown as the pixel circuit.

Each of the patterns of the transistor TFT and the capacitor Cst may beformed through a deposition process of the conductive layer or thesemiconductor layer, a photolithography process of the conductive layeror the semiconductor layer, and an etching process of the conductivelayer or the semiconductor layer. Each of the insulating layers 10 br,10 bf, 10, 20, 30, 40, and 50 may be formed by a deposition process ofan inorganic material or an organic material.

Referring to FIG. 7A, the stopper pattern STP and the first electrode AEmay be formed on the fifth insulating layer 50, for example by forming aconductive layer and patterning it using a photolithography process andan etching process. The conductive layer may have the multi-layerstructure of ITO/Ag/ITO.

Then, as shown in FIG. 7B, the pixel definition layer PDL may be formedon the fifth insulating layer 50 to cover the stopper pattern STP andthe first electrode AE. The first opening P-OP1 may be defined throughthe pixel definition layer PDL to expose the first electrode AE.

In the present embodiment, the pixel definition layer PDL may include anegative photosensitive resin material. After a negative photosensitiveresin layer is formed, the negative photosensitive resin layer may beexposed and developed using a halftone mask, and thus, the pixeldefinition layer PDL may be patterned. Portions of the negativephotosensitive resin layer, which are not exposed, may be removedthrough an etching process. As a result of the above process, the pixeldefinition layer PDL divided into a plurality of areas may be formed.

The first opening P-OP1 may be formed by a light blocking area of thehalftone mask, the first area P-A1 may be formed by an opening area ofthe halftone mask, and the second area P-A2 that is partially removedmay overlap a slit area or a gradation area of the halftone mask. In thepresent embodiment, the negative photosensitive resin material isdescribed as a representative example. However, the present disclosureshould not be limited to the negative photosensitive resin material. Thepixel definition layer PDL may include a positive photosensitive resinmaterial.

Referring to FIG. 7C, a mask pattern MSP through which an etchingopening MSP-OP is defined corresponding to the stopper pattern STP maybe formed on the pixel definition layer PDL. The mask pattern MSP mayinclude a transparent conductive oxide. The mask pattern MSP may includeindium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zincoxide (IGZO), zinc oxide (ZnOx), indium oxide (In2O3), or aluminum-dopedzinc oxide (AZO).

After a transparent conductive oxide layer is formed, the etchingopening MSP-OP may be formed through the transparent conductive oxidelayer using a photolithography process and an etching process.

Referring to FIG. 7D, the second opening P-OP2 may be formed through thepixel definition layer PDL using the mask pattern MSP to expose thestopper pattern STP. The pixel definition layer PDL and the mask patternMSP may have different etch rates with respect to an etchant or anetching gas. For instance, the pixel definition layer PDL may be etchedusing oxygen plasma, but the mask pattern MSP including a metal materialmay not be etched by the oxygen plasma. Accordingly, the etching of thepixel definition layer PDL may be stopped by the stopper pattern STP,and the depth of the second opening P-OP2 may be determined by thestopper pattern STP.

Referring to FIG. 7E, the mask pattern MSP is removed. The mask patternMSP may be removed by an etching process. A portion of the stopperpattern STP may be etched in the process of removing the mask patternMSP. For instance, an upper transparent conductive oxide layer of thestopper pattern STP having the multi-layer structure may be etched.

Referring to FIG. 7F, the second electrode CE may be formed after thelight emitting layer EL is formed. The light emitting layer EL may beformed through a deposition process using a mask through which anopening is formed corresponding to the light emitting area LA. Then, thesecond electrode CE entirely overlapping the display area DD-DA (referto FIG. 1A) is formed through a deposition process using an open mask.

Then, the thin film encapsulation layer 140 may be formed. The inorganiclayer 141 may be formed through a deposition process using an open maskto entirely overlap the display area DD-DA (refer to FIG. 1A). Theorganic layer 142 may be formed through an inkjet process. In addition,the inorganic layer 143 may be formed through a deposition process usingan open mask to entirely overlap the display area DD-DA (refer to FIG.1A).

FIGS. 8 and 9 are cross-sectional views of a display panel according toembodiments of the present disclosure. Hereinafter, the cross-sectionalviews of FIGS. 8 to 9 are shown with respect to the cross-section ofFIG. 6 , and in FIGS. 8 to 9 , detailed descriptions of the componentsdescribed with reference to FIG. 6 to 7F will be omitted.

Referring to FIG. 8 , a location of a stopper pattern STP1 may bechanged. The stopper pattern STP1 may be disposed under a firstelectrode AE and may be formed prior to the first electrode AE. Thestopper pattern STP1 may be disposed on the same layer as a layer onwhich one of connection electrodes CNE1 and CNE2 are disposed. Thestopper pattern STP1 may be formed through the same process as theconnection electrodes CNE1 and CNE2, may include the same material asthe connection electrodes CNE1 and CNE2, and may have the same stackstructure as the connection electrodes CNE1 and CNE2. In FIG. 8 , thestopper pattern STP1 disposed on the same layer as the second connectionelectrode CNE2 is shown as a representative example.

FIG. 9 shows two types of stopper patterns STP and STP2. A first stopperpattern STP may be substantially the same as the stopper pattern STP ofFIG. 6 . The second stopper pattern STP2 may be disposed under a firstelectrode AE and may be formed prior to the first electrode AE.

Referring to FIG. 9 , the second stopper pattern STP2 may be disposed onthe same layer as a layer on which the gate GT1 is disposed. The secondstopper pattern STP2 may be formed through the same process as the gateGT1, may include the same material as the gate GT1, and may have thesame stack structure as the gate GT1.

Referring to FIGS. 8 and 9 , as some stopper patterns STP1 and STP2 aredisposed under a fifth insulating layer 50, a depth of a second openingP-OP2 overlapping the stopper patterns STP1 and STP2 may increase. Thesecond opening P-OP2 overlapping the stopper patterns STP1 and STP2 mayfurther penetrate through the fifth insulating layer 50. In FIGS. 8 and9 , the second opening P-OP2 of the second area P-A2, which has thedepth greater than that of the second opening P-OP2 of the second areaP-A2 of FIG. 6 , is shown. The second opening P-OP2 with the increaseddepth may increase a coupling force of the inorganic layer 141.

Although the embodiments of the present disclosure have been described,it is understood that the present disclosure should not be limited tothese embodiments but various changes and modifications can be made byone ordinary skilled in the art within the spirit and scope of thepresent disclosure as hereinafter claimed.

Therefore, the disclosed subject matter should not be limited to anysingle embodiment described herein, and the scope of the presentinventive concept shall be determined according to the attached claims.

What is claimed is:
 1. A display device comprising: a display panel, thedisplay panel comprising: a transistor; an insulating layer disposed onthe transistor; a light emitting element electrically connected to thetransistor and comprising a first electrode disposed on the insulatinglayer, a light emitting layer disposed on the first electrode, and asecond electrode disposed on the light emitting layer; a stopper patterndisposed spaced apart from the first electrode; a pixel definition layerdisposed on the stopper pattern and having a first opening extendingthrough the pixel definition layer to the first electrode and a secondopening extending through the pixel definition layer to the stopperpattern; and a thin film encapsulation layer disposed on the pixeldefinition layer and inside the second opening, and covering the lightemitting element.
 2. The display device of claim 1, wherein the stopperpattern is disposed on the insulating layer and comprises a samematerial as the first electrode.
 3. The display device of claim 2,wherein the stopper pattern has a same layered structure as the firstelectrode.
 4. The display device of claim 1, wherein the secondelectrode is disposed inside the second opening.
 5. The display deviceof claim 1, wherein the thin film encapsulation layer comprises: a firstinorganic layer; an organic layer disposed on the first inorganic layer;and a second inorganic layer disposed on the organic layer.
 6. Thedisplay device of claim 1, wherein the stopper pattern is provided inplural, the second opening is provided in plural, and there is one ofthe stopper patterns at a base of the second openings.
 7. The displaydevice of claim 1, wherein the light emitting element comprises aplurality of first color light emitting elements, a plurality of secondcolor light emitting elements, and a plurality of third color lightemitting elements, and the stopper pattern is disposed in anon-light-emitting area defined between one light emitting element amongthe first color light emitting elements, the second light emittingelements adjacent to each other among the second color light emittingelements, and one light emitting element among the third color lightemitting elements.
 8. The display device of claim 7, wherein the stopperpattern is provided in plural, and two or more stopper patterns aredisposed in the non-light-emitting area.
 9. The display device of claim1, wherein the pixel definition layer comprises: a first area having afirst thickness; and a second area having a second thickness smallerthan the first thickness, and the second opening is defined in each ofthe first area and the second area.
 10. The display device of claim 9,wherein the second opening defined in the second area further extendsthrough the insulating layer.
 11. The display device of claim 1, whereinthe second opening has a depth greater than a width.
 12. The displaydevice of claim 1, further comprising a connection electrode disposedbetween the transistor and the light emitting element and electricallyconnected to the transistor and the light emitting element, wherein thestopper pattern is disposed under the insulating layer and comprises asame material as the connection electrode.
 13. The display device ofclaim 1, wherein the transistor comprises a semiconductor pattern and agate, and the stopper pattern is disposed under the insulating layer andcomprises a same material as the gate.
 14. The display device of claim1, further comprising an input sensor disposed on the display panel. 15.The display device of claim 14, further comprising an anti-reflectiveunit disposed on the input sensor, wherein the anti-reflective unitcomprises a color filter overlapping the first opening and a lightblocking pattern overlapping the second opening.
 16. A method ofmanufacturing a display device, comprising: forming a stopper patternmade of a conductive material on an insulating layer; forming a firstelectrode of a light emitting element spaced apart from the stopperpattern; forming a pixel definition layer on the insulating layer, thestopper pattern, and the first electrode; forming a first openingthrough the pixel definition layer to expose the first electrode of thelight emitting element and remove some of the pixel definition layercovering the stopper pattern; providing a mask pattern on the pixeldefinition layer, wherein the mask pattern has an etching opening thatcorresponds to the stopper pattern; forming a second opening through thepixel definition layer to expose the stopper pattern; removing the maskpattern; forming a light emitting layer and a second electrode on thefirst electrode of the light emitting element; and forming a thin filmencapsulation layer on the second electrode, wherein the stopper patternis formed prior to the first electrode of the light emitting element oris formed through a same process as the first electrode of the lightemitting element.
 17. The method of claim 16, wherein the mask patterncomprises a transparent conductive oxide.
 18. The method of claim 16,wherein the second electrode is disposed inside the second opening. 19.The method of claim 16, further comprising forming an inorganic layer onthe second electrode and inside the second opening.
 20. The method ofclaim 16, further comprising: forming a transistor; and forming aconnection electrode electrically connected to the transistor and thefirst electrode of the light emitting element, wherein the stopperpattern is formed through a same process as a gate of the transistor orthe connection electrode.